Multi-port memories are commonly used to transfer data among different synchronous systems that are asynchronous with respect to each other. An example of such a memory is a dual-port synchronous random access memory (SRAM) as shown in FIG. 1. In FIG. 1, the dual-port memory 100 has a left port and a right port. The left port has a data bus 101, an address bus 103, a control line 105 and a status line 107. The signals on these buses and lines are synchronous to a left clock (LCLK) 109. Similarly, the right port has a data bus 102, an address bus 104, a control line 106 and a status line 108. The signals on these buses and lines are synchronous to a right clock (RCLK) 110. There is no relationship between the left clock (LCLK) and the right clock (RCLK); they are asynchronous with respect to each other.
When the ports access different memory locations in the dual port memory 100, even at overlapping times, data can be written to or read from the memory by each port as if the other port did not exist. There is no memory address contention and the transfer of data takes place normally. However, when both ports try to access the same memory location at the same time, the data at that location might have an unexpected content. For example, if one port is trying to read a memory location while the other is writing to the memory location, the read data may be old data, new data or even corrupted data based on the timing of the internal read cycle. One way to avoid this problem is to have a mechanism for deciding which port, among contending ports, will be granted either sole or priority access to the memory address location, and to notify the other ports of the results. This process is referred to as arbitration.
FIG. 2 illustrates an arbitration path 200 in a conventional dual port memory, where the left port is attempting to write to a memory location and the right port is attempting to read from the same memory location. For simplicity, FIG. 2 assumes that the left port loses the arbitration so only the affected left port write control path is illustrated. In FIG. 2, the left port address is clocked into register 201 and the right port address is clocked into register 202. The exclusive OR gate 203 represents a filter that detects left port and right port address matches and passes them on to arbiter core cell 204 for timing arbitration. The arbiter core cell 204 is typically an RS flip-flop with fast recovery time from meta-stable conditions. Clock delay elements 205 are used to insert timing delays greater than or equal to the setup time of arbiter core cell 204. The nominal data-in to arbitration-out time of the arbiter core cell is pushed out if the address match arrival time on one of its inputs violates the setup time with respect to the other. In the example shown, the arbitration result (L_BUSY) is used to clear register 206 when it is clocked by the delayed LCLK signal 109. Absent the arbitration result, left port address 103 would be logically AND'd with the left port write enable signal 207 and clocked into register 208. The critical nature of the timing for this path is shown by the typical propagation and setting time delays (in nanoseconds) for the individual components in the path. As illustrated in FIG. 2, the total delay for this path from input register 201 (or 202) to output register 208, including clock skew, is 1.9 nanoseconds. In a double data rate (DDR) memory, for example, this delay would limit the maximum clock frequency to 263 Mhz without dropping clock cycles.
In addition to the read-write scenario described above, arbitration may be required when multiple ports are attempting to read the same memory location and when multiple ports are attempting to write to the same memory location. In the first case, if too many ports are allowed to read the same memory location at once, enough read current maybe drawn from the memory cell to de-stabilize it. In this case, an arbitration process might allow access by only one port or a limited number of ports, block access by all other ports and provide a busy signal on the status line of each blocked port. In the second case, only one port can be allowed to write to a memory location at one time, because otherwise the data will be corrupted. All other ports should be blocked from writing to the memory, and notified via a status signal. This latter arbitration function, blocking write operations, is one of the most critical timing paths in multi-port memory designs because the asynchronous clock domains create meta-stable conditions that require extra time to resolve, and address setup violations that can result in large timing pushouts, wasting memory cycles.